| SPECIFICATIONS (Rev. B 04/22/11) |
| Frequency |
4320 – 4930 MHz |
| Step Size |
1 MHz |
| Reference Input Frequency |
10 MHz1 |
| Reference Input Voltage |
1.0 V p-p to 3.0 V p-p |
| Bias Voltage |
| Vcc (Vdc) |
V (Vdc) |
I (mA Max.) |
| VCO |
+5 |
55 |
| Digital |
+3 |
18 |
| Tune |
+12 |
5 |
| Output Power |
+5 dBm (Min.) |
| Spurious Suppression |
-68 dB (Typ.) |
| Harmonic Suppression |
45 dB (Typ.) |
| Setting Time |
3 mSec (Typ.)2 |
| Output Impedance |
50 Ohms (Nom.) |
| Lock Detect Indicator |
CMOS 3.0 V |
| Typical Phase Noise |
| Offset |
Phase Noise |
| @ 10 kHz |
-85 dBc/Hz |
| @ 100 kHz |
-102 dBc/Hz |
| Operating Temperature Range |
-40 to +85 °C |
| Programming |
See Application Note: AN7500 |
1 Reference input frequency is programmable (see AN7500) in multiples of the step size, 10 MHz is the factory default setting. 150 MHz (Max.)
2 From the rising edge of LE to stable lock detect |
| Absolute Maximum Ratings |
| Storage Temp. Range |
-55 to +125 °C |
| Bias Voltage (Digital) |
+3.6 V |
| Bias Voltage (VCO) |
+5.5 V |
| Bias Voltage (Tune) |
+25.5 V |
| DC Voltage Applied to RF Out |
±25 V |
