| SPECIFICATIONS (Rev. N 04/08/11) |
| Frequency |
600 – 1700 MHz |
| Step Size |
500 kHz |
| Reference Input Frequency |
10 MHz1 |
| Input Voltage |
1.0 V p-p to 3.3 V p-p |
| Bias Voltage |
| Vcc (Vdc) |
V (Vdc) |
I (mA Max.) |
| Digital |
+5 |
65 |
| VCO |
+5 |
40 |
| Converter |
+5 |
55 |
| Output Power |
+5 dBm (Min.) |
| Spurious Suppression |
75 dB (Typ.) |
| Harmonic Suppression |
12 dB (Typ.) |
| Settling Time |
10 mSec (Typ.)2 |
| Output Impedance |
50 Ohms (Nom.) |
| Lock Detect Indicator |
CMOS 3.3 V |
| Typical Phase Noise |
| Offset |
Phase Noise |
| @ 1 kHz |
-92 dBc/Hz |
| @ 10 kHz |
-90 dBc/Hz |
| @ 100 kHz |
-118 dBc/Hz |
| Operating Temperature Range |
-40 to +85 °C |
| Programming |
See Application Note: AN100 |
1 Reference input frequency is programmable (See AN100) in multiples of the step size, 10 MHz is the factory default setting. 150 MHz (Max.)
2 From the rising edge of LE to stable lock detect |
| Absolute Maximum Ratings |
| Storage Temp. Range |
-55 to +125 °C |
| Bias Voltage (Digital) |
+5.25 V |
| Bias Voltage (VCO) |
+5.5 V |
| Bias Voltage (Converter) |
+5.5 V |
| DC Voltage Applied to RF Out |
±25 V |
